How To Load Numbers Into A Gpio Register

STM32duino GPIO Registers and Programming

Fleck Setting in C

Setting a scrap

Use the bitwise OR operator ( | ) to set a scrap.

That will set flake ten.

Immigration a bit

Employ the bitwise AND operator (&) to articulate a fleck.

That will articulate bit x. You must invert the bit string with the bitwise NOT operator (~), then AND information technology.

Toggling a chip

The XOR operator (^) can be used to toggle a fleck.

That volition toggle fleck x.

Checking a flake

To check a flake, shift the number x to the right, and so bitwise AND it:

That will put the value of bit x into the variable fleck.

Changing the nth flake to 10

Setting the nth chip to either i or 0 can be accomplished with the following:

number ^= (-x ^ number) & (1              << north);

Chip due north will be gear up if x is 1, and cleared if x is 0.

GPIO Registers

The libmaple libraries, on which STM32duino is based, provides access to registers by the syntax:

where REG tin can be ane of the post-obit:

CRH and CRL

CRH is used to ready type/and or speed of pins 8-15 of the port.
CRL is used to fix type/and or speed of pins 0-7 of the port.
Accessed every bit a 32 chip word, with 4 $.25 representing the country of each pivot. Out of these 4 $.25, the low 2 bits are Way, and high 2 bits are CNF.

The iv bits for each pin can be set to:
0b0011 (binary) or 0x3 (HEX) - Corresponds to setting pin as output, same as pinMode()
0b1000 or 0x8 - Corresponds to setting pin as input, same every bit pinMode()

Say I desire to fix PORTA pins 0, iii and iv to OUTPUT and 1, six, 7 to INPUT, and go out pins 2 and 5 in their original state. The code is:

PORTA->regs->CRL = (PORTA->regs->CRL &              0x00F00F00) |              0x88000080              |0x00033003;                              //0x00F00F00 is bitmask to retain value of pins two and 5 in original state                              //0x88000080 is bitmask to ready inputs                              //0x00033003 is bitmask to set outputs            

IDR - Input Information Register

Used to read input of entire 16 pins of port at one time. Accessed every bit a 32 fleck word whose lower 16 bits stand for each pivot. The pins being read must be fix to INPUT way by using CRL/CRH or pinMode() before using this.

Say I want to read pins A2. The lawmaking is:

              bool              result = GPIOA->regs->IDR &              0x0004;                              //returns true if A2 is Loftier                              //0x0004 is 0b0000000000000100            

ODR - Output Data Register

Used to write output to entire 16 pins of port at once. Accessed and written as a 32 bit give-and-take whose lower 16 bits stand for each pivot. The pins beingness read must be set to OUTPUT mode by using CRL/CRH or pinMode() earlier using this.

Say I want to set pins A2, A12 and A13, and reset (clear) all other pins in the xvi pin bus. The lawmaking is:

GPIOA->regs->ODR =              0b0011000000000100;                              //note,  binary            

Now if I want to gear up and clear A2, A12 and A13 without altering other pins, the lawmaking is:

                              //Prepare A2, A12, A13 (HIGH)              GPIOA->regs->ODR |=              0b0011000000000100;                              //Clear A2, A12, A13 (LOW)              GPIOA->regs->ODR &= ~(0b0011000000000100);

but observe how, if we desire to touch only some pins, we have to READ, MASK and WRITE. That's why in that location is BRR and BSRR

BRR - Bit Reset Register

32 bit word. Lower 16 $.25 have i'south where $.25 are to be ready to "Low". Upper 16 bits have ane's where bits are to exist set "Loftier". 0's mean ignore

Now, to set and clear A2, A12, A13 while preserving the land of all other pins in the port, the code is:

                              //Set A2, A12, A13 (High)              GPIOA->regs->BRR =              0b0011000000000100              <<              sixteen;                              //motility to upper sixteen bits                              //Clear A2, A12, A13 (LOW)              GPIOA->regs->BRR =              0b0011000000000100;

BSRR - Scrap Fix Reset Register

BSRR is like the complement of BRR. It's likewise a 32 bit word. Lower 16 $.25 take 1's where bits are to be prepare to "Loftier". Upper 16 bits have 1's where bits are to be set "LOW". 0'due south mean ignore

In this example, to set and articulate A2, A12, A13 while preserving the land of all other pins in the port, the code is:

                              //Set A2, A12, A13 (High)              GPIOA->regs->BSRR =              0b0011000000000100;                              //Clear A2, A12, A13 (LOW)              GPIOA->regs->BSRR =              0b0011000000000100              <<              16;                              //move to upper 16 $.25            

Combination of BRR and BSRR

Since BRR and BSRR are opposite of each other, you tin can employ both if you don't want to do the bit shift left operation .

In this case, to ready and clear A2, A12, A13 while preserving the state of all other pins in the port, the lawmaking is:

                              //Set A2, A12, A13 (HIGH)              GPIOA->regs->BSRR =              0b0011000000000100;                              //lower 16 bits                              //Clear A2, A12, A13 (Low)              GPIOA->regs->BRR =              0b0011000000000100;                              //lower 16 bits            

Sources:

• http://embedded-lab.com/blog/stm32-gpio-ports-insights/
• http://hertaville.com/stm32f0-gpio-tutorial-function-1.html
• http://stackoverflow.com/questions/47981/how-do-you lot-gear up-clear-and-toggle-a-single-bit-in-c-c?rq=1
• https://gist.github.com/iwalpola/6c36c9573fd322a268ce890a118571ca

How To Load Numbers Into A Gpio Register,

Source: https://gist.github.com/Vitorbnc/e35f1ff1485d660edf365241dacfa387

Posted by: gonzalezpreen1992.blogspot.com

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